Static timing analysis (STA) is a method to determine the timing performance of a digital circuit design by checking all the possible path for timing violations under worst case conditions.
STA provides faster and simpler way of checking and analysing all the timing parts in the design for any timing violations.
1. What is a latch and a flipflop?
Latch and Flipflop are memory elements that are used in sequential designs. A latch is level triggered memory element and a flipflop is an edge triggered memory element.
2. What is setup time and hold time?
Setup time and hold time are the timing parameters of a flipflop.
Setup time: The minimum time required for the data to be stable before the clock edge.
Hold time: The minimum time required for the data to be stable after the clock edge.
3. What is Arrival Time (AT) and Required Arrival Time (RAT)?
Arrival Time: It is the time taken by data to travel through the data path.
Required Arrival Time: It is the time taken for the clock to travel through the clock path.
4. What are the various paths in a sequential circuit?
There are totally 4 different paths.
Path 1: Input to Register path
Path 2: Register to Register path
Path 3: Register to Output path
Path 4: Input to Output path
5. What is critical path?
Critical path is a path in the sequential design with the longest delay. It includes all the combinational gates, memory elements and all. For a critical path, the logic is not considered.
There might be critical paths which are found in the design, and they are logically invalid. This is because, while finding the critical paths, all the elements are considered as black blocks with known delay. There might be critical paths which are not logically valid, and they are called False paths.
6. What is maximum clock frequency?
Maximum clock frequency (fmax) is the highest frequency at which a digital circuit can operate reliably without violating timing constraints. It is determined by the longest delay path (critical path) in the circuit. This critical path includes the combinational logic delay, setup time, and any clock skew.
Calculating Maximum Clock Frequency
Identify the Critical Path: Determine the path in the circuit with the longest propagation delay from one sequential element (e.g., flip-flop) to another.
Calculate the Total Delay on the Critical Path: Sum up the delays of all the logic gates and interconnects on the critical path.
Include Setup Time and Clock Skew: Add the setup time required by the destination flip-flop and any clock skew (the difference in arrival times of the clock signal at different parts of the circuit).
Given:
Tcrict: Critical path delay, which includes combinational delay, setup time, and clock skew.
The clock period (T) must satisfy the following condition to ensure no setup time violations:
T ≥ Tcrict
The maximum clock frequency is then given by the inverse of the clock period:
fmax = 1/Tcrict
7. What is Clock skew?
Clock skew refers to the difference in arrival times of the same clock signal at the clock pins of two different flip-flops within a circuit design.
8. In a given sequential circuit, how do you find the maximum clock frequency?
In a given sequential circuit, the clock frequency is calculated for the critical path. The delays of all the elements and setup time of the flipflops on the critical path are the used to calculate the clock frequency.
To calculate the clock frequency, one must need to find Arrival time and Required Arrival time. For that, tcq, tcomb, tsu, tskew must be known.
Arrival time = tcq + tcomb
Required Arrival time = Tclk + tskew - tsu
RAT should be greater than AT to not have any violations. From that we get
Tclk > tcq + tcomb + tsu – tskew
fmax = 1/Tclk
9. What is slack? What is its importance?
Slack is the measure of time difference between AT and RAT which gives information about how much amount of delay can be reduced or introduced without any violations.
For setup analysis: Slack = RAT – AT = (Tclk + tskew - tsu) – (tcq + tcomb)
For hold analysis: Slack = AT – RAT = (Tclk + tcq + tcomb) – (Tclk + tskew + thold)
If setup slack is positive, there is no violation. Else there is violation.
10. What is setup time violation? What causes it?
In a sequential design, RAT for setup > AT for no setup violation.
Arrival time = tcq + tcomb
Required Arrival time = Tclk + tskew - tsu
RAT > AT is the setup condition.
11. What is hold time violation? What causes it?
In a sequential design, RAT for hold < AT for no hold violation.
Arrival time = Tclk + tcq + tcomb
Required Arrival time = Tclk + tskew + thold
RAT < AT is the hold condition.
12. What factors affect the setup time and hold time?
Setup time and hold time are the intrinsic parameters of a flipflop which are highly dependent on the topology and the design on the flipflop.
13. How to avoid setup violation and hold violation?
tcomb, tskew are responsible for the setup and hold violation. These need to be altered in order to avoid any violation.
tcq and tskew also matter for setup violation, but they cannot be controlled by a designer.
Further if Tclk is allowed to be altered, then it can also be altered to avoid violations.
14. What are the non-idealities of a clock signal? What factors affect the non-idealities of the clock?
Clock signal is generated from a single crystal at one point and distributed over the entire chip. The interconnects for the wire are long enough to produce some delays in the clock signals from one flipflop to other. This is called Clock Skew (unintentional). The clock signal is not always ideal with respect to the phase. It will have some temporal variations from the ideal edges. This is called Clock Jitter. This is caused either by the noise in the clock oscillator or the other disturbances in the circuit like power supply noise, thermal noise etc.
There are many factors or sources that produce these non-idealities in the clock signal.
15. How does the clock skew and clock jitter affect the setup conditions and hold conditions?
In the presence of clock skew and clock jitter, the RAT and AT for setup and hold conditions will change.
For Setup condition:
Arrival time = tcq + tcomb
Required Arrival time = Tclk + tskew - tsu – 2tjitter
For Hold condition:
Arrival time = Tclk + tcq + tcomb
Required Arrival time = Tclk + tskew + thold + 2tjitter
16. How to avoid the clock skew (unintentional)?
The clock skew caused by the interconnects can be avoided by adding the inverters where is no delay.
As there is a clock skew of 3ns, we need to insert an inverter with a delay of 3ns in Path1. This will make the clock signal to be at the same instant in both the paths.
Static timing analysis (STA) is a method to determine the timing performance of a digital circuit design by checking all the possible path for timing violations under worst case conditions.
STA provides faster and simpler way of checking and analysing all the timing parts in the design for any timing violations.
1. What is a latch and a flipflop?
Latch and Flipflop are memory elements that are used in sequential designs. A latch is level triggered memory element and a flipflop is an edge triggered memory element.
2. What is setup time and hold time?
Setup time and hold time are the timing parameters of a flipflop.
Setup time: The minimum time required for the data to be stable before the clock edge.
Hold time: The minimum time required for the data to be stable after the clock edge.
3. What is Arrival Time (AT) and Required Arrival Time (RAT)?
Arrival Time: It is the time taken by data to travel through the data path.
Required Arrival Time: It is the time taken for the clock to travel through the clock path.
4. What are the various paths in a sequential circuit?
There are totally 4 different paths.
Path 1: Input to Register path
Path 2: Register to Register path
Path 3: Register to Output path
Path 4: Input to Output path
5. What is critical path?
Critical path is a path in the sequential design with the longest delay. It includes all the combinational gates, memory elements and all. For a critical path, the logic is not considered.
There might be critical paths which are found in the design, and they are logically invalid. This is because, while finding the critical paths, all the elements are considered as black blocks with known delay. There might be critical paths which are not logically valid, and they are called False paths.
6. What is maximum clock frequency?
Maximum clock frequency (fmax) is the highest frequency at which a digital circuit can operate reliably without violating timing constraints. It is determined by the longest delay path (critical path) in the circuit. This critical path includes the combinational logic delay, setup time, and any clock skew.
Calculating Maximum Clock Frequency
Identify the Critical Path: Determine the path in the circuit with the longest propagation delay from one sequential element (e.g., flip-flop) to another.
Calculate the Total Delay on the Critical Path: Sum up the delays of all the logic gates and interconnects on the critical path.
Include Setup Time and Clock Skew: Add the setup time required by the destination flip-flop and any clock skew (the difference in arrival times of the clock signal at different parts of the circuit).
Given:
Tcrict: Critical path delay, which includes combinational delay, setup time, and clock skew.
The clock period (T) must satisfy the following condition to ensure no setup time violations:
T ≥ Tcrict
The maximum clock frequency is then given by the inverse of the clock period:
fmax = 1/Tcrict
7. What is Clock skew?
Clock skew refers to the difference in arrival times of the same clock signal at the clock pins of two different flip-flops within a circuit design.
8. In a given sequential circuit, how do you find the maximum clock frequency?
In a given sequential circuit, the clock frequency is calculated for the critical path. The delays of all the elements and setup time of the flipflops on the critical path are the used to calculate the clock frequency.
To calculate the clock frequency, one must need to find Arrival time and Required Arrival time. For that, tcq, tcomb, tsu, tskew must be known.
Arrival time = tcq + tcomb
Required Arrival time = Tclk + tskew - tsu
RAT should be greater than AT to not have any violations. From that we get
Tclk > tcq + tcomb + tsu – tskew
fmax = 1/Tclk
9. What is slack? What is its importance?
Slack is the measure of time difference between AT and RAT which gives information about how much amount of delay can be reduced or introduced without any violations.
For setup analysis: Slack = RAT – AT = (Tclk + tskew - tsu) – (tcq + tcomb)
For hold analysis: Slack = AT – RAT = (Tclk + tcq + tcomb) – (Tclk + tskew + thold)
If setup slack is positive, there is no violation. Else there is violation.
10. What is setup time violation? What causes it?
In a sequential design, RAT for setup > AT for no setup violation.
Arrival time = tcq + tcomb
Required Arrival time = Tclk + tskew - tsu
RAT > AT is the setup condition.
11. What is hold time violation? What causes it?
In a sequential design, RAT for hold < AT for no hold violation.
Arrival time = Tclk + tcq + tcomb
Required Arrival time = Tclk + tskew + thold
RAT < AT is the hold condition.
12. What factors affect the setup time and hold time?
Setup time and hold time are the intrinsic parameters of a flipflop which are highly dependent on the topology and the design on the flipflop.
13. How to avoid setup violation and hold violation?
tcomb, tskew are responsible for the setup and hold violation. These need to be altered in order to avoid any violation.
tcq and tskew also matter for setup violation, but they cannot be controlled by a designer.
Further if Tclk is allowed to be altered, then it can also be altered to avoid violations.
14. What are the non-idealities of a clock signal? What factors affect the non-idealities of the clock?
Clock signal is generated from a single crystal at one point and distributed over the entire chip. The interconnects for the wire are long enough to produce some delays in the clock signals from one flipflop to other. This is called Clock Skew (unintentional). The clock signal is not always ideal with respect to the phase. It will have some temporal variations from the ideal edges. This is called Clock Jitter. This is caused either by the noise in the clock oscillator or the other disturbances in the circuit like power supply noise, thermal noise etc.
There are many factors or sources that produce these non-idealities in the clock signal.
15. How does the clock skew and clock jitter affect the setup conditions and hold conditions?
In the presence of clock skew and clock jitter, the RAT and AT for setup and hold conditions will change.
For Setup condition:
Arrival time = tcq + tcomb
Required Arrival time = Tclk + tskew - tsu – 2tjitter
For Hold condition:
Arrival time = Tclk + tcq + tcomb
Required Arrival time = Tclk + tskew + thold + 2tjitter
16. How to avoid the clock skew (unintentional)?
The clock skew caused by the interconnects can be avoided by adding the inverters where is no delay.
As there is a clock skew of 3ns, we need to insert an inverter with a delay of 3ns in Path1. This will make the clock signal to be at the same instant in both the paths.
0 Comments