Hardware Description Languages (HDLs) are specialized computer languages used to program electronic and digital logic circuits. High level languages with which we can specify our hardware to analyse its design before actual fabrication.
Two most popular HDLs:
Verilog and VHDL
Other popular HDLs:
SystemC, SystemVerilog and other…
1. What do you understand from Verilog?
Verilog is a hardware description language (HDL) used to model and design digital systems. It allows designers to describe the structure and behavior of electronic circuits, facilitating the simulation, verification, and synthesis of hardware.
2. What are the data types in Verilog? Key differences between Reg and Wire and their default values.
A variable in Verilog can be
Net type: wire, wor, wand, tri, supply0, supply1, etc.
Register type: reg, integer, real, time
Key differences between reg and wire:
reg (Register) | wire (Net) |
Retains the last value assigned to it. | Must be continuously driven, cannot be used to store value. |
Usually used to represent storage elements. | Models connections between continuous assignments and instantiations |
May or may not map to hardware register during synthesis. | 1-bit values by default, unless declared as vector explicitly |
Default Values | |
The default value of a reg variable is x (unknown). | The default value of a wire variable is z (high-impedance or high-Z). |
3. What are the different modeling styles in Verilog? Or What are different level of abstraction in Verilog?
Mainly there are three modeling styles or levels of abstraction in Verilog. Let’s understand with an example of Full Adder.
1) Structural Modeling: Structural modeling describes a system by specifying its components and their interconnections. It is like creating a schematic diagram in code form.
Characteristics:
- Low-level abstraction.
- Uses module instances to represent components.
- Emphasizes the physical structure of the system.
Use Cases:
- Detailed design of hardware components.
- Creating and testing complex digital systems by interconnecting simpler modules.
2) Dataflow Modeling: Dataflow modeling describes the flow of data and the operations performed on it. This style uses continuous assignments and is typically used to describe combinational logic.
Characteristics:
- Medium level of abstraction.
- Uses assign statements to represent continuous assignments.
- Emphasizes the relationships between inputs and outputs
Use Cases:
- Describing combinational circuits like multiplexers, adders, and ALUs.
- Situations where clear data flow representation is needed.
3) Behavioral Modeling: Behavioral modeling describes the functionality of a digital system without specifying its structure. It's used to design and simulate complex systems by focusing on what the system does rather than how it does it.
Characteristics:
- High-level abstraction.
- Utilizes always blocks and initial blocks.
- Uses constructs like if, case, for, while, etc.
Use Cases:
- Designing complex control logic.
- Initial stages of design for simulation and verification.
4. Difference between Inter and Intra assignment delays.
Delays are non-synthesizable – used in testbench.
Inter-assignment delays specify the time between the execution of two separate assignments. They delay the subsequent assignment statement by a specified amount of time.
Intra-assignment delays introduce a delay within a single assignment statement. The right-hand side (RHS) of the assignment is evaluated immediately, but the assignment to the left-hand side (LHS) is delayed.
Inter-assignment | #5 a= b | #5; a = b; | Waits 5-time units before assigning b to a |
Intra-assignment | a = #5 b; | temp = b; #5; a = temp; | After 5-time units, assign the value of b to a |
5. What is the difference between blocking and non-blocking in Verilog? Can we mix both the statements.
Blocking Assignments | Non-blocking Assignments |
Blocking assignments (= operator) in Verilog are executed sequentially in the order they appear in the code. | Non-blocking assignments (<= operator) in Verilog are executed concurrently and do not block the execution of subsequent statements. |
When a blocking assignment is encountered, the next statement will not be executed until the current assignment is completed. | Non-blocking assignments schedule the updates to occur in the next simulation time step, allowing for parallel execution of statements. |
Blocking assignments are commonly used in combinational logic to model concurrent behavior, where the order of execution is critical. | Non-blocking assignments are commonly used in sequential logic to model clocked behavior, where updates to state variables occur synchronously with a clock edge. |
In combinational logic, all statements are executed concurrently, and the final value of a signal depends on the order of assignments. | In sequential logic, updates to state variables occur in parallel but take effect only after the current time step has completed, reflecting the behavior of real hardware. |
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Can we mix both the statements?
Yes, you can mix blocking (=) and non-blocking (<=) assignments in Verilog, but it is important to use them appropriately to avoid unintended behavior.
Avoid Mixing in Sequential Logic: Avoid mixing blocking and non-blocking assignments within the same always block when modeling sequential logic (e.g., flip-flops). This can lead to race conditions and unexpected behavior.
Safe Usage: Use blocking assignments for combinational logic and non-blocking assignments for sequential logic to ensure predictable simulation results.
6. What is the difference between == and === in Verilog?
In Verilog, == and === are both comparison operators, but they serve different purposes and have distinct behaviors, especially when dealing with unknown or high-impedance states.
| == (Equality Operator) | === (Case Equality Operator) | |
Purpose | Used for logical equality comparison. | Used for case equality comparison. | |
Behavior | Compare two operands bit by bit.
| Compares two operands bit by bit, including unknown (x) and high-impedance (z) values. | |
Unknown(x) or high impedance(z) handling | Treats unknown (x) and high-impedance (z) values as non-deterministic, meaning any comparison involving x or z can lead to an unknown result. | Compares two operands bit by bit, including unknown (x) and high-impedance (z) values.
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Use Cases | |||
Typically used in conditional statements where exact matching (excluding unknowns) is needed | Useful in scenarios where exact bitwise matching is required, including handling of unknown and high-impedance states. | ||
Common in combinational logic and control flow statements. | Often used in test benches and verification where precise comparison is necessary. | ||
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Example:
a | b | a==b | a===b |
4’b1010 | 4’b1010 | 1 (true) | 1 (true) |
4’b1010 | 4’b1011 | 0 (false) | 0 (false) |
4’b1010 | 4’b10x0 | x (unknown) | 0 (false) |
4’b1010 | 4’b10z0 | x (unknown) | 0 (false) |
4’b1010 | 3’b101 | 0 (false) | 0 (false) |
4’b1010 | 10 | 1 (true) | 1 (true) |
4’b10x0 | 4’b10x0 | x (unknown) | 1 (true) |
4’b10z0 | 4’10z0 | X (unknown) | 1 (true) |
7. What do the case, casex and casez statements do in Verilog?
Verilog provides three variations of the case statement: case, casex, and casez. Each handles x and z values differently.
case: Matches exact values, considering x and z as they are. Executes default if no match.
casex: Treats x and z as don't-care, matching any value in those positions.
casez: Treats z (or ?) as don't-care, matching any value in those positions.
8. What is compiler Directive? Difference between `define and `include.
A compiler directive is a statement in the source code that provides instructions to the compiler about how to process the code. These directives are not part of the program's logic but guide the compilation process.
`define is for defining macros or constants, while `include is for including external files into the current file. Both are crucial for writing clean, maintainable Verilog code.
9. What is `timescale? What does `timescale 1 ns/ 1 ps in a Verilog code?
It is a ‘compile directive’ and is used for the measurement of simulation time and delay.
Syntax: `timescale <time_unit>/<time_precision>
time_unit: Measurement for simulation time and delay.
time_precision: Rounding the simulation time values means the simulator can at least advance by a specified value.
Examples:
`timescale 1ns/1ns: Since precision = 1ns, the simulator will advance its time if the delay value is greater or equal to 0.5ns. Thus, time advancement does not happen for 0.45ns delay.
`timescale 1ns/1ps: Since precision = 1ps, the simulator will advance for all the cases
10. Write a Verilog code for D-Latch and Flip-Flop.
The main difference between the D Latch and D Flip-Flop lies in the data capture mechanism:
D Latch: Captures data on the positive edge of the clock.
D Flip-Flop: Captures data with a delay after the positive edge of the clock (ensuring setup time is met).
11. Write a Verilog Program to switch the Contents of two Registers: With and Without a Temporary Register.
Using an extra register | Without using an extra register |
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12. What are synchronous and asynchronous resets? Explain it using DFF and write their Verilog code?
Synchronous Reset | Asynchronous Reset |
Synchronous reset ensures a controlled reset operation synchronized with the system clock. | Asynchronous reset allows for immediate reset without regard to the clock signal. |
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